First commit.
This commit is contained in:
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#ifndef __INC_CLOCKLESS_ARM_NRF51
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#define __INC_CLOCKLESS_ARM_NRF51
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#if defined(NRF51)
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#include <nrf51_bitfields.h>
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#define FASTLED_HAS_CLOCKLESS 1
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#if (FASTLED_ALLOW_INTERRUPTS==1)
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#define SEI_CHK LED_TIMER->CC[0] = (WAIT_TIME * (F_CPU/1000000)); LED_TIMER->TASKS_CLEAR; LED_TIMER->EVENTS_COMPARE[0] = 0;
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#define CLI_CHK cli(); if(LED_TIMER->EVENTS_COMPARE[0]) { LED_TIMER->TASKS_STOP = 1; return 0; }
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#define INNER_SEI sei();
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#else
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#define SEI_CHK
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#define CLI_CHK
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#define INNER_SEI delaycycles<1>();
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#endif
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#include "../common/m0clockless.h"
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template <uint8_t DATA_PIN, int T1, int T2, int T3, EOrder RGB_ORDER = RGB, int XTRA0 = 0, bool FLIP = false, int WAIT_TIME = 75>
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class ClocklessController : public CPixelLEDController<RGB_ORDER> {
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typedef typename FastPinBB<DATA_PIN>::port_ptr_t data_ptr_t;
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typedef typename FastPinBB<DATA_PIN>::port_t data_t;
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data_t mPinMask;
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data_ptr_t mPort;
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CMinWait<WAIT_TIME> mWait;
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public:
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virtual void init() {
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FastPinBB<DATA_PIN>::setOutput();
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mPinMask = FastPinBB<DATA_PIN>::mask();
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mPort = FastPinBB<DATA_PIN>::port();
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}
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virtual uint16_t getMaxRefreshRate() const { return 400; }
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virtual void showPixels(PixelController<RGB_ORDER> & pixels) {
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mWait.wait();
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cli();
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if(!showRGBInternal(pixels)) {
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sei(); delayMicroseconds(WAIT_TIME); cli();
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showRGBInternal(pixels);
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}
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sei();
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mWait.mark();
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}
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// This method is made static to force making register Y available to use for data on AVR - if the method is non-static, then
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// gcc will use register Y for the this pointer.
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static uint32_t showRGBInternal(PixelController<RGB_ORDER> pixels) {
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struct M0ClocklessData data;
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data.d[0] = pixels.d[0];
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data.d[1] = pixels.d[1];
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data.d[2] = pixels.d[2];
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data.s[0] = pixels.mScale[0];
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data.s[1] = pixels.mScale[1];
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data.s[2] = pixels.mScale[2];
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data.e[0] = pixels.e[0];
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data.e[1] = pixels.e[1];
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data.e[2] = pixels.e[2];
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data.adj = pixels.mAdvance;
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typename FastPin<DATA_PIN>::port_ptr_t portBase = FastPin<DATA_PIN>::port();
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// timer mode w/prescaler of 0
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LED_TIMER->MODE = TIMER_MODE_MODE_Timer;
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LED_TIMER->PRESCALER = 0;
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LED_TIMER->EVENTS_COMPARE[0] = 0;
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LED_TIMER->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
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LED_TIMER->SHORTS = TIMER_SHORTS_COMPARE0_CLEAR_Msk;
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LED_TIMER->TASKS_START = 1;
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int ret = showLedData<4,8,T1,T2,T3,RGB_ORDER,WAIT_TIME>(portBase, FastPin<DATA_PIN>::mask(), pixels.mData, pixels.mLen, &data);
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LED_TIMER->TASKS_STOP = 1;
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return ret; // 0x00FFFFFF - _VAL;
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}
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};
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#endif // NRF51
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#endif // __INC_CLOCKLESS_ARM_NRF51
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@ -0,0 +1,9 @@
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#ifndef __INC_FASTLED_ARM_NRF51_H
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#define __INC_FASTLED_ARM_NRF51_H
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// Include the k20 headers
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#include "fastpin_arm_nrf51.h"
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#include "fastspi_arm_nrf51.h"
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#include "clockless_arm_nrf51.h"
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#endif
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@ -0,0 +1,119 @@
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#ifndef __FASTPIN_ARM_NRF51_H
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#define __FASTPIN_ARM_NRF51_H
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#if defined(NRF51)
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/// Template definition for teensy 3.0 style ARM pins, providing direct access to the various GPIO registers. Note that this
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/// uses the full port GPIO registers. In theory, in some way, bit-band register access -should- be faster, however I have found
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/// that something about the way gcc does register allocation results in the bit-band code being slower. It will need more fine tuning.
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/// The registers are data output, set output, clear output, toggle output, input, and direction
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#if 0
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template<uint8_t PIN, uint32_t _MASK, typename _DIRSET, typename _DIRCLR, typename _OUTSET, typename _OUTCLR, typename _OUT> class _ARMPIN {
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public:
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typedef volatile uint32_t * port_ptr_t;
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typedef uint32_t port_t;
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inline static void setOutput() { _DIRSET::r() = _MASK; }
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inline static void setInput() { _DIRCLR::r() = _MASK; }
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inline static void hi() __attribute__ ((always_inline)) { _OUTSET::r() = _MASK; }
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inline static void lo() __attribute__ ((always_inline)) { _OUTCLR::r() = _MASK; }
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inline static void set(register port_t val) __attribute__ ((always_inline)) { _OUT::r() = val; }
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inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
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inline static void toggle() __attribute__ ((always_inline)) { _OUT::r() ^= _MASK; }
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inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
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inline static void lo(register port_ptr_t port) __attribute__ ((always_inline)) { lo(); }
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inline static void fastset(register port_ptr_t port, register port_t val) __attribute__ ((always_inline)) { *port = val; }
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inline static port_t hival() __attribute__ ((always_inline)) { return _OUT::r() | _MASK; }
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inline static port_t loval() __attribute__ ((always_inline)) { return _OUT::r() & ~_MASK; }
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inline static port_ptr_t port() __attribute__ ((always_inline)) { return &_OUT::r(); }
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inline static port_t mask() __attribute__ ((always_inline)) { return _MASK; }
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};
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#define ADDR(X) *(volatile uint32_t*)X
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#define NR_GPIO_ADDR(base,offset) (*(volatile uint32_t *))((uint32_t)(base + offset))
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#define NR_DIRSET ADDR(0x50000518UL) // NR_GPIO_ADDR(NRF_GPIO_BASE, 0x518)
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#define NR_DIRCLR ADDR(0x5000051CUL) // NR_GPIO_ADDR(NRF_GPIO_BASE, 0x51C)
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#define NR_OUTSET ADDR(0x50000508UL) // NR_GPIO_ADDR(NRF_GPIO_BASE, 0x508)
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#define NR_OUTCLR ADDR(0x5000050CUL) // NR_GPIO_ADDR(NRF_GPIO_BASE, 0x50C)
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#define NR_OUT ADDR(0x50000504UL) // NR_GPIO_ADDR(NRF_GPIO_BASE, 0x504)
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#define _RD32_NRF(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; }};
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_RD32_NRF(NR_DIRSET);
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_RD32_NRF(NR_DIRCLR);
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_RD32_NRF(NR_OUTSET);
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_RD32_NRF(NR_OUTCLR);
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_RD32_NRF(NR_OUT);
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#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN, \
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_R(NR_DIRSET), _R(NR_DIRCLR), _R(NR_OUTSET), _R(NR_OUTCLR), _R(NR_OUT)> {};
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#else
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typedef struct { /*!< GPIO Structure */
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// __I uint32_t RESERVED0[321];
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__IO uint32_t OUT; /*!< Write GPIO port. */
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__IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
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__IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
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__I uint32_t IN; /*!< Read GPIO port. */
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__IO uint32_t DIR; /*!< Direction of GPIO pins. */
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__IO uint32_t DIRSET; /*!< DIR set register. */
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__IO uint32_t DIRCLR; /*!< DIR clear register. */
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__I uint32_t RESERVED1[120];
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__IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
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} FL_NRF_GPIO_Type;
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#define FL_NRF_GPIO_BASE 0x50000504UL
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#define FL_NRF_GPIO ((FL_NRF_GPIO_Type *) FL_NRF_GPIO_BASE)
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template<uint8_t PIN, uint32_t _MASK> class _ARMPIN {
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public:
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typedef volatile uint32_t * port_ptr_t;
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typedef uint32_t port_t;
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inline static void setOutput() { FL_NRF_GPIO->DIRSET = _MASK; }
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inline static void setInput() { FL_NRF_GPIO->DIRCLR = _MASK; }
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inline static void hi() __attribute__ ((always_inline)) { FL_NRF_GPIO->OUTSET = _MASK; }
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inline static void lo() __attribute__ ((always_inline)) { FL_NRF_GPIO->OUTCLR= _MASK; }
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inline static void set(register port_t val) __attribute__ ((always_inline)) { FL_NRF_GPIO->OUT = val; }
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inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
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inline static void toggle() __attribute__ ((always_inline)) { FL_NRF_GPIO->OUT ^= _MASK; }
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inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
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inline static void lo(register port_ptr_t port) __attribute__ ((always_inline)) { lo(); }
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inline static void fastset(register port_ptr_t port, register port_t val) __attribute__ ((always_inline)) { *port = val; }
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inline static port_t hival() __attribute__ ((always_inline)) { return FL_NRF_GPIO->OUT | _MASK; }
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inline static port_t loval() __attribute__ ((always_inline)) { return FL_NRF_GPIO->OUT & ~_MASK; }
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inline static port_ptr_t port() __attribute__ ((always_inline)) { return &FL_NRF_GPIO->OUT; }
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inline static port_t mask() __attribute__ ((always_inline)) { return _MASK; }
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inline static bool isset() __attribute__ ((always_inline)) { return (FL_NRF_GPIO->IN & _MASK) != 0; }
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};
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#define _FL_DEFPIN(PIN) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << PIN> {};
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#endif
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// Actual pin definitions
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#define MAX_PIN 31
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_FL_DEFPIN(0); _FL_DEFPIN(1); _FL_DEFPIN(2); _FL_DEFPIN(3);
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_FL_DEFPIN(4); _FL_DEFPIN(5); _FL_DEFPIN(6); _FL_DEFPIN(7);
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_FL_DEFPIN(8); _FL_DEFPIN(9); _FL_DEFPIN(10); _FL_DEFPIN(11);
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_FL_DEFPIN(12); _FL_DEFPIN(13); _FL_DEFPIN(14); _FL_DEFPIN(15);
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_FL_DEFPIN(16); _FL_DEFPIN(17); _FL_DEFPIN(18); _FL_DEFPIN(19);
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_FL_DEFPIN(20); _FL_DEFPIN(21); _FL_DEFPIN(22); _FL_DEFPIN(23);
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_FL_DEFPIN(24); _FL_DEFPIN(25); _FL_DEFPIN(26); _FL_DEFPIN(27);
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_FL_DEFPIN(28); _FL_DEFPIN(29); _FL_DEFPIN(30); _FL_DEFPIN(31);
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#define HAS_HARDWARE_PIN_SUPPORT
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#endif
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#endif
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@ -0,0 +1,150 @@
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#ifndef __INC_FASTSPI_NRF_H
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#define __INC_FASTSPI_NRF_H
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#ifdef NRF51
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#ifndef FASTLED_FORCE_SOFTWARE_SPI
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#define FASTLED_ALL_PINS_HARDWARE_SPI
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// A nop/stub class, mostly to show the SPI methods that are needed/used by the various SPI chipset implementations. Should
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// be used as a definition for the set of methods that the spi implementation classes should use (since C++ doesn't support the
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// idea of interfaces - it's possible this could be done with virtual classes, need to decide if i want that overhead)
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template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint32_t _SPI_CLOCK_DIVIDER>
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class NRF51SPIOutput {
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struct saveData {
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uint32_t sck;
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uint32_t mosi;
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uint32_t miso;
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uint32_t freq;
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uint32_t enable;
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} mSavedData;
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void saveSPIData() {
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mSavedData.sck = NRF_SPI0->PSELSCK;
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mSavedData.mosi = NRF_SPI0->PSELMOSI;
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mSavedData.miso = NRF_SPI0->PSELMISO;
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mSavedData.freq = NRF_SPI0->FREQUENCY;
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mSavedData.enable = NRF_SPI0->ENABLE;
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}
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void restoreSPIData() {
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NRF_SPI0->PSELSCK = mSavedData.sck;
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NRF_SPI0->PSELMOSI = mSavedData.mosi;
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NRF_SPI0->PSELMISO = mSavedData.miso;
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NRF_SPI0->FREQUENCY = mSavedData.freq;
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mSavedData.enable = NRF_SPI0->ENABLE;
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}
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public:
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NRF51SPIOutput() { FastPin<_DATA_PIN>::setOutput(); FastPin<_CLOCK_PIN>::setOutput(); }
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NRF51SPIOutput(Selectable *pSelect) { FastPin<_DATA_PIN>::setOutput(); FastPin<_CLOCK_PIN>::setOutput(); }
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// set the object representing the selectable
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void setSelect(Selectable *pSelect) { /* TODO */ }
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// initialize the SPI subssytem
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void init() {
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FastPin<_DATA_PIN>::setOutput();
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FastPin<_CLOCK_PIN>::setOutput();
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NRF_SPI0->PSELSCK = _CLOCK_PIN;
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NRF_SPI0->PSELMOSI = _DATA_PIN;
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NRF_SPI0->PSELMISO = 0xFFFFFFFF;
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NRF_SPI0->FREQUENCY = 0x80000000;
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NRF_SPI0->ENABLE = 1;
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NRF_SPI0->EVENTS_READY = 0;
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}
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// latch the CS select
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void select() { saveSPIData(); init(); }
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// release the CS select
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void release() { shouldWait(); restoreSPIData(); }
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static bool shouldWait(bool wait = false) __attribute__((always_inline)) __attribute__((always_inline)) {
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// static bool sWait=false;
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// bool oldWait = sWait;
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// sWait = wait;
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// never going to bother with waiting since we're always running the spi clock at max speed on the rfduino
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// TODO: When we set clock rate, implement/fix waiting properly, otherwise the world hangs up
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return false;
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}
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// wait until all queued up data has been written
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static void waitFully() __attribute__((always_inline)){ if(shouldWait()) { while(NRF_SPI0->EVENTS_READY==0); } NRF_SPI0->INTENCLR; }
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static void wait() __attribute__((always_inline)){ if(shouldWait()) { while(NRF_SPI0->EVENTS_READY==0); } NRF_SPI0->INTENCLR; }
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// write a byte out via SPI (returns immediately on writing register)
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static void writeByte(uint8_t b) __attribute__((always_inline)) { wait(); NRF_SPI0->TXD = b; NRF_SPI0->INTENCLR; shouldWait(true); }
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// write a word out via SPI (returns immediately on writing register)
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static void writeWord(uint16_t w) __attribute__((always_inline)){ writeByte(w>>8); writeByte(w & 0xFF); }
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// A raw set of writing byte values, assumes setup/init/waiting done elsewhere (static for use by adjustment classes)
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static void writeBytesValueRaw(uint8_t value, int len) { while(len--) { writeByte(value); } }
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// A full cycle of writing a value for len bytes, including select, release, and waiting
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void writeBytesValue(uint8_t value, int len) {
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select();
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while(len--) {
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writeByte(value);
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}
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waitFully();
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release();
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}
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// A full cycle of writing a raw block of data out, including select, release, and waiting
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template<class D> void writeBytes(uint8_t *data, int len) {
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uint8_t *end = data + len;
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select();
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while(data != end) {
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writeByte(D::adjust(*data++));
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}
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D::postBlock(len);
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waitFully();
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release();
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}
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void writeBytes(uint8_t *data, int len) {
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writeBytes<DATA_NOP>(data, len);
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}
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// write a single bit out, which bit from the passed in byte is determined by template parameter
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template <uint8_t BIT> inline static void writeBit(uint8_t b) {
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waitFully();
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NRF_SPI0->ENABLE = 0;
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if(b & 1<<BIT) {
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FastPin<_DATA_PIN>::hi();
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} else {
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FastPin<_DATA_PIN>::lo();
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}
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FastPin<_CLOCK_PIN>::toggle();
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FastPin<_CLOCK_PIN>::toggle();
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NRF_SPI0->ENABLE = 1;
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}
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template <uint8_t FLAGS, class D, EOrder RGB_ORDER> void writePixels(PixelController<RGB_ORDER> pixels) {
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select();
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int len = pixels.mLen;
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while(pixels.has(1)) {
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if(FLAGS & FLAG_START_BIT) {
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writeBit<0>(1);
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}
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writeByte(D::adjust(pixels.loadAndScale0()));
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writeByte(D::adjust(pixels.loadAndScale1()));
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writeByte(D::adjust(pixels.loadAndScale2()));
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pixels.advanceData();
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pixels.stepDithering();
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}
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D::postBlock(len);
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waitFully();
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release();
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}
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};
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#endif
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#endif
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#endif
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@ -0,0 +1,46 @@
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#ifndef __LED_SYSDEFS_ARM_NRF51
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#define __LED_SYSDEFS_ARM_NRF51
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#ifndef NRF51
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#define NRF51
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#endif
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#define LED_TIMER NRF_TIMER1
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#define FASTLED_NO_PINMAP
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#define FASTLED_HAS_CLOCKLESS
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#define FASTLED_SPI_BYTE_ONLY
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#define FASTLED_ARM
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#define FASTLED_ARM_M0
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#ifndef F_CPU
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#define F_CPU 16000000
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#endif
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#include <stdint.h>
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#include <nrf51.h>
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#include <core_cm0.h>
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||||
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typedef volatile uint32_t RoReg;
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typedef volatile uint32_t RwReg;
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typedef uint32_t prog_uint32_t;
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typedef uint8_t boolean;
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||||
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#define PROGMEM
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#define NO_PROGMEM
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#define NEED_CXX_BITS
|
||||
|
||||
// Default to NOT using PROGMEM here
|
||||
#ifndef FASTLED_USE_PROGMEM
|
||||
#define FASTLED_USE_PROGMEM 0
|
||||
#endif
|
||||
|
||||
#ifndef FASTLED_ALLOW_INTERRUPTS
|
||||
#define FASTLED_ALLOW_INTERRUPTS 1
|
||||
#endif
|
||||
|
||||
#define cli() __disable_irq();
|
||||
#define sei() __enable_irq();
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user