468 lines
22 KiB
C++
468 lines
22 KiB
C++
#ifndef __INC_CLOCKLESS_TRINKET_H
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#define __INC_CLOCKLESS_TRINKET_H
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#include "../../controller.h"
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#include "../../lib8tion.h"
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#include <avr/interrupt.h> // for cli/se definitions
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FASTLED_NAMESPACE_BEGIN
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#if defined(FASTLED_AVR)
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// Scaling macro choice
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#ifndef TRINKET_SCALE
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#define TRINKET_SCALE 1
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// whether or not to use dithering
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#define DITHER 1
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#endif
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#if (F_CPU==8000000)
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#define FASTLED_SLOW_CLOCK_ADJUST // asm __volatile__ ("mov r0,r0\n\t");
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#else
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#define FASTLED_SLOW_CLOCK_ADJUST
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#endif
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#define US_PER_TICK (64 / (F_CPU/1000000))
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// Variations on the functions in delay.h - w/a loop var passed in to preserve registers across calls by the optimizer/compiler
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template<int CYCLES> inline void _dc(register uint8_t & loopvar);
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template<int _LOOP, int PAD> __attribute__((always_inline)) inline void _dc_AVR(register uint8_t & loopvar) {
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_dc<PAD>(loopvar);
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// The convolution in here is to ensure that the state of the carry flag coming into the delay loop is preserved
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asm __volatile__ ( "BRCS L_PC%=\n\t"
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" LDI %[loopvar], %[_LOOP]\n\tL_%=: DEC %[loopvar]\n\t BRNE L_%=\n\tBREQ L_DONE%=\n\t"
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"L_PC%=: LDI %[loopvar], %[_LOOP]\n\tLL_%=: DEC %[loopvar]\n\t BRNE LL_%=\n\tBSET 0\n\t"
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"L_DONE%=:\n\t"
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:
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[loopvar] "+a" (loopvar) : [_LOOP] "M" (_LOOP) : );
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}
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template<int CYCLES> __attribute__((always_inline)) inline void _dc(register uint8_t & loopvar) {
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_dc_AVR<CYCLES/6,CYCLES%6>(loopvar);
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}
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template<> __attribute__((always_inline)) inline void _dc<-6>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc<-5>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc<-4>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc<-3>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc<-2>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc<-1>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc< 0>(register uint8_t & ) {}
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template<> __attribute__((always_inline)) inline void _dc< 1>(register uint8_t & ) {asm __volatile__("mov r0,r0":::);}
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template<> __attribute__((always_inline)) inline void _dc< 2>(register uint8_t & ) {asm __volatile__("rjmp .+0":::);}
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template<> __attribute__((always_inline)) inline void _dc< 3>(register uint8_t & loopvar) { _dc<2>(loopvar); _dc<1>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc< 4>(register uint8_t & loopvar) { _dc<2>(loopvar); _dc<2>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc< 5>(register uint8_t & loopvar) { _dc<2>(loopvar); _dc<3>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc< 6>(register uint8_t & loopvar) { _dc<2>(loopvar); _dc<2>(loopvar); _dc<2>(loopvar);}
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template<> __attribute__((always_inline)) inline void _dc< 7>(register uint8_t & loopvar) { _dc<4>(loopvar); _dc<3>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc< 8>(register uint8_t & loopvar) { _dc<4>(loopvar); _dc<4>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc< 9>(register uint8_t & loopvar) { _dc<5>(loopvar); _dc<4>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<10>(register uint8_t & loopvar) { _dc<6>(loopvar); _dc<4>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<11>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<1>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<12>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<2>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<13>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<3>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<14>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<4>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<15>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<5>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<16>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<6>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<17>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<7>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<18>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<8>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<19>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<9>(loopvar); }
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template<> __attribute__((always_inline)) inline void _dc<20>(register uint8_t & loopvar) { _dc<10>(loopvar); _dc<10>(loopvar); }
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#define DINTPIN(T,ADJ,PINADJ) (T-(PINADJ+ADJ)>0) ? _dc<T-(PINADJ+ADJ)>(loopvar) : _dc<0>(loopvar);
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#define DINT(T,ADJ) if(AVR_PIN_CYCLES(DATA_PIN)==1) { DINTPIN(T,ADJ,1) } else { DINTPIN(T,ADJ,2); }
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#define _D1(ADJ) DINT(T1,ADJ)
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#define _D2(ADJ) DINT(T2,ADJ)
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#define _D3(ADJ) DINT(T3,ADJ)
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//
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// Base template for clockless controllers. These controllers have 3 control points in their cycle for each bit. The first point
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// is where the line is raised hi. The second point is where the line is dropped low for a zero. The third point is where the
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// line is dropped low for a one. T1, T2, and T3 correspond to the timings for those three in clock cycles.
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//
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#if (!defined(NO_CORRECTION) || (NO_CORRECTION == 0)) && (FASTLED_ALLOW_INTERRUPTS == 0)
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static uint8_t gTimeErrorAccum256ths;
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#endif
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#define FASTLED_HAS_CLOCKLESS 1
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template <uint8_t DATA_PIN, int T1, int T2, int T3, EOrder RGB_ORDER = RGB, int XTRA0 = 0, bool FLIP = false, int WAIT_TIME = 10>
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class ClocklessController : public CPixelLEDController<RGB_ORDER> {
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static_assert(T1 >= 2 && T2 >= 2 && T3 >= 3, "Not enough cycles - use a higher clock speed");
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typedef typename FastPin<DATA_PIN>::port_ptr_t data_ptr_t;
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typedef typename FastPin<DATA_PIN>::port_t data_t;
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CMinWait<WAIT_TIME> mWait;
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public:
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virtual void init() {
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FastPin<DATA_PIN>::setOutput();
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}
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virtual uint16_t getMaxRefreshRate() const { return 400; }
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protected:
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virtual void showPixels(PixelController<RGB_ORDER> & pixels) {
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mWait.wait();
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cli();
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showRGBInternal(pixels);
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// Adjust the timer
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#if (!defined(NO_CORRECTION) || (NO_CORRECTION == 0)) && (FASTLED_ALLOW_INTERRUPTS == 0)
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uint32_t microsTaken = (uint32_t)pixels.size() * (uint32_t)CLKS_TO_MICROS(24 * (T1 + T2 + T3));
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// adust for approximate observed actal runtime (as of January 2015)
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// roughly 9.6 cycles per pixel, which is 0.6us/pixel at 16MHz
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// microsTaken += nLeds * 0.6 * CLKS_TO_MICROS(16);
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microsTaken += scale16by8(pixels.size(),(0.6 * 256) + 1) * CLKS_TO_MICROS(16);
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// if less than 1000us, there is NO timer impact,
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// this is because the ONE interrupt that might come in while interrupts
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// are disabled is queued up, and it will be serviced as soon as
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// interrupts are re-enabled.
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// This actually should technically also account for the runtime of the
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// interrupt handler itself, but we're just not going to worry about that.
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if( microsTaken > 1000) {
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// Since up to one timer tick will be queued, we don't need
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// to adjust the MS_COUNTER for that one.
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microsTaken -= 1000;
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// Now convert microseconds to 256ths of a second, approximately like this:
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// 250ths = (us/4)
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// 256ths = 250ths * (263/256);
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uint16_t x256ths = microsTaken >> 2;
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x256ths += scale16by8(x256ths,7);
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x256ths += gTimeErrorAccum256ths;
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MS_COUNTER += (x256ths >> 8);
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gTimeErrorAccum256ths = x256ths & 0xFF;
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}
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#if 0
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// For pixel counts of 30 and under at 16Mhz, no correction is necessary.
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// For pixel counts of 15 and under at 8Mhz, no correction is necessary.
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//
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// This code, below, is smaller, and quicker clock correction, which drifts much
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// more significantly, but is a few bytes smaller. Presented here for consideration
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// as an alternate on the ATtiny, which can't have more than about 150 pixels MAX
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// anyway, meaning that microsTaken will never be more than about 4,500, which fits in
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// a 16-bit variable. The difference between /1000 and /1024 only starts showing
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// up in the range of about 100 pixels, so many ATtiny projects won't even
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// see a clock difference due to the approximation there.
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uint16_t microsTaken = (uint32_t)nLeds * (uint32_t)CLKS_TO_MICROS((24) * (T1 + T2 + T3));
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MS_COUNTER += (microsTaken >> 10);
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#endif
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#endif
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sei();
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mWait.mark();
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}
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#define USE_ASM_MACROS
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// The variables that our various asm statemetns use. The same block of variables needs to be declared for
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// all the asm blocks because GCC is pretty stupid and it would clobber variables happily or optimize code away too aggressively
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#define ASM_VARS : /* write variables */ \
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[count] "+x" (count), \
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[data] "+z" (data), \
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[b1] "+a" (b1), \
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[d0] "+r" (d0), \
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[d1] "+r" (d1), \
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[d2] "+r" (d2), \
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[loopvar] "+a" (loopvar), \
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[scale_base] "+a" (scale_base) \
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: /* use variables */ \
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[ADV] "r" (advanceBy), \
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[b0] "a" (b0), \
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[hi] "r" (hi), \
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[lo] "r" (lo), \
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[s0] "r" (s0), \
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[s1] "r" (s1), \
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[s2] "r" (s2), \
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[e0] "r" (e0), \
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[e1] "r" (e1), \
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[e2] "r" (e2), \
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[PORT] "M" (FastPin<DATA_PIN>::port()-0x20), \
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[O0] "M" (RGB_BYTE0(RGB_ORDER)), \
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[O1] "M" (RGB_BYTE1(RGB_ORDER)), \
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[O2] "M" (RGB_BYTE2(RGB_ORDER)) \
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: "cc" /* clobber registers */
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// Note: the code in the else in HI1/LO1 will be turned into an sts (2 cycle, 2 word) opcode
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// 1 cycle, write hi to the port
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#define HI1 FASTLED_SLOW_CLOCK_ADJUST if((int)(FastPin<DATA_PIN>::port())-0x20 < 64) { asm __volatile__("out %[PORT], %[hi]" ASM_VARS ); } else { *FastPin<DATA_PIN>::port()=hi; }
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// 1 cycle, write lo to the port
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#define LO1 if((int)(FastPin<DATA_PIN>::port())-0x20 < 64) { asm __volatile__("out %[PORT], %[lo]" ASM_VARS ); } else { *FastPin<DATA_PIN>::port()=lo; }
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// 2 cycles, sbrs on flipping the line to lo if we're pushing out a 0
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#define QLO2(B, N) asm __volatile__("sbrs %[" #B "], " #N ASM_VARS ); LO1;
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// load a byte from ram into the given var with the given offset
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#define LD2(B,O) asm __volatile__("ldd %[" #B "], Z + %[" #O "]\n\t" ASM_VARS );
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// 4 cycles - load a byte from ram into the scaling scratch space with the given offset, clear the target var, clear carry
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#define LDSCL4(B,O) asm __volatile__("ldd %[scale_base], Z + %[" #O "]\n\tclr %[" #B "]\n\tclc\n\t" ASM_VARS );
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#if (DITHER==1)
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// apply dithering value before we do anything with scale_base
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#define PRESCALE4(D) asm __volatile__("cpse %[scale_base], __zero_reg__\n\t add %[scale_base],%[" #D "]\n\tbrcc L_%=\n\tldi %[scale_base], 0xFF\n\tL_%=:\n\t" ASM_VARS);
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// Do the add for the prescale
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#define PRESCALEA2(D) asm __volatile__("cpse %[scale_base], __zero_reg__\n\t add %[scale_base],%[" #D "]\n\t" ASM_VARS);
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// Do the clamp for the prescale, clear carry when we're done - NOTE: Must ensure carry flag state is preserved!
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#define PRESCALEB4(D) asm __volatile__("brcc L_%=\n\tldi %[scale_base], 0xFF\n\tL_%=:\n\tneg %[" #D "]\n\tCLC" ASM_VARS);
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// Clamp for prescale, increment data, since we won't ever wrap 65k, this also effectively clears carry for us
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#define PSBIDATA4(D) asm __volatile__("brcc L_%=\n\tldi %[scale_base], 0xFF\n\tL_%=:\n\tadd %A[data], %[ADV]\n\tadc %B[data], __zero_reg__\n\t" ASM_VARS);
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#else
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#define PRESCALE4(D) _dc<4>(loopvar);
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#define PRESCALEA2(D) _dc<2>(loopvar);
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#define PRESCALEB4(D) _dc<4>(loopvar);
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#define PSBIDATA4(D) asm __volatile__( "add %A[data], %[ADV]\n\tadc %B[data], __zero_reg__\n\trjmp .+0\n\t" ASM_VARS );
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#endif
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// 2 cycles - perform one step of the scaling (if a given bit is set in scale, add scale-base to the scratch space)
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#define _SCALE02(B, N) "sbrc %[s0], " #N "\n\tadd %[" #B "], %[scale_base]\n\t"
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#define _SCALE12(B, N) "sbrc %[s1], " #N "\n\tadd %[" #B "], %[scale_base]\n\t"
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#define _SCALE22(B, N) "sbrc %[s2], " #N "\n\tadd %[" #B "], %[scale_base]\n\t"
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#define SCALE02(B,N) asm __volatile__( _SCALE02(B,N) ASM_VARS );
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#define SCALE12(B,N) asm __volatile__( _SCALE12(B,N) ASM_VARS );
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#define SCALE22(B,N) asm __volatile__( _SCALE22(B,N) ASM_VARS );
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// 1 cycle - rotate right, pulling in from carry
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#define _ROR1(B) "ror %[" #B "]\n\t"
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#define ROR1(B) asm __volatile__( _ROR1(B) ASM_VARS);
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// 1 cycle, clear the carry bit
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#define _CLC1 "clc\n\t"
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#define CLC1 asm __volatile__( _CLC1 ASM_VARS );
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// 2 cycles, rortate right, pulling in from carry then clear the carry bit
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#define RORCLC2(B) asm __volatile__( _ROR1(B) _CLC1 ASM_VARS );
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// 4 cycles, rotate, clear carry, scale next bit
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#define RORSC04(B, N) asm __volatile__( _ROR1(B) _CLC1 _SCALE02(B, N) ASM_VARS );
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#define RORSC14(B, N) asm __volatile__( _ROR1(B) _CLC1 _SCALE12(B, N) ASM_VARS );
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#define RORSC24(B, N) asm __volatile__( _ROR1(B) _CLC1 _SCALE22(B, N) ASM_VARS );
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// 4 cycles, scale bit, rotate, clear carry
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#define SCROR04(B, N) asm __volatile__( _SCALE02(B,N) _ROR1(B) _CLC1 ASM_VARS );
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#define SCROR14(B, N) asm __volatile__( _SCALE12(B,N) _ROR1(B) _CLC1 ASM_VARS );
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#define SCROR24(B, N) asm __volatile__( _SCALE22(B,N) _ROR1(B) _CLC1 ASM_VARS );
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/////////////////////////////////////////////////////////////////////////////////////
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// Loop life cycle
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// dither adjustment macro - should be kept in sync w/what's in stepDithering
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// #define ADJDITHER2(D, E) D = E - D;
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#define _NEGD1(D) "neg %[" #D "]\n\t"
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#define _ADJD1(D,E) "add %[" #D "], %[" #E "]\n\t"
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#define ADJDITHER2(D, E) asm __volatile__ ( _NEGD1(D) _ADJD1(D, E) ASM_VARS);
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#define ADDDE1(D, E) asm __volatile__ ( _ADJD1(D, E) ASM_VARS );
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// #define xstr(a) str(a)
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// #define str(a) #a
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// #define ADJDITHER2(D,E) asm __volatile__("subi %[" #D "], " xstr(DUSE) "\n\tand %[" #D "], %[" #E "]\n\t" ASM_VARS);
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// define the beginning of the loop
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#define LOOP asm __volatile__("1:" ASM_VARS );
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// define the end of the loop
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#define DONE asm __volatile__("2:" ASM_VARS );
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// 2 cycles - increment the data pointer
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#define IDATA2 asm __volatile__("add %A[data], %[ADV]\n\tadc %B[data], __zero_reg__\n\t" ASM_VARS );
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#define IDATACLC3 asm __volatile__("add %A[data], %[ADV]\n\tadc %B[data], __zero_reg__\n\t" _CLC1 ASM_VARS );
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// 1 cycle mov
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#define _MOV1(B1, B2) "mov %[" #B1 "], %[" #B2 "]\n\t"
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#define MOV1(B1, B2) asm __volatile__( _MOV1(B1,B2) ASM_VARS );
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// 3 cycle mov - skip if scale fix is happening
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#if (FASTLED_SCALE8_FIXED == 1)
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#define _MOV_FIX03(B1, B2) "mov %[" #B1 "], %[scale_base]\n\tcpse %[s0], __zero_reg__\n\t" _MOV1(B1, B2)
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#define _MOV_FIX13(B1, B2) "mov %[" #B1 "], %[scale_base]\n\tcpse %[s1], __zero_reg__\n\t" _MOV1(B1, B2)
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#define _MOV_FIX23(B1, B2) "mov %[" #B1 "], %[scale_base]\n\tcpse %[s2], __zero_reg__\n\t" _MOV1(B1, B2)
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#else
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// if we haven't fixed scale8, just do the move and nop the 2 cycles that would be used to
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// do the fixed adjustment
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#define _MOV_FIX03(B1, B2) _MOV1(B1, B2) "rjmp .+0\n\t"
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#define _MOV_FIX13(B1, B2) _MOV1(B1, B2) "rjmp .+0\n\t"
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#define _MOV_FIX23(B1, B2) _MOV1(B1, B2) "rjmp .+0\n\t"
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#endif
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// 3 cycle mov + negate D for dither adjustment
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#define MOV_NEGD04(B1, B2, D) asm __volatile( _MOV_FIX03(B1, B2) _NEGD1(D) ASM_VARS );
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#define MOV_ADDDE04(B1, B2, D, E) asm __volatile( _MOV_FIX03(B1, B2) _ADJD1(D, E) ASM_VARS );
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#define MOV_NEGD14(B1, B2, D) asm __volatile( _MOV_FIX13(B1, B2) _NEGD1(D) ASM_VARS );
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#define MOV_ADDDE14(B1, B2, D, E) asm __volatile( _MOV_FIX13(B1, B2) _ADJD1(D, E) ASM_VARS );
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#define MOV_NEGD24(B1, B2, D) asm __volatile( _MOV_FIX23(B1, B2) _NEGD1(D) ASM_VARS );
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// 2 cycles - decrement the counter
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#define DCOUNT2 asm __volatile__("sbiw %[count], 1" ASM_VARS );
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// 2 cycles - jump to the beginning of the loop
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#define JMPLOOP2 asm __volatile__("rjmp 1b" ASM_VARS );
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// 2 cycles - jump out of the loop
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#define BRLOOP1 asm __volatile__("brne 3\n\trjmp 2f\n\t3:" ASM_VARS );
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// 5 cycles 2 sbiw, 3 for the breq/rjmp
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#define ENDLOOP5 asm __volatile__("sbiw %[count], 1\n\tbreq L_%=\n\trjmp 1b\n\tL_%=:\n\t" ASM_VARS);
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// NOP using the variables, forcing a move
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#define DNOP asm __volatile__("mov r0,r0" ASM_VARS);
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#define DADVANCE 3
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#define DUSE (0xFF - (DADVANCE-1))
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// Silence compiler warnings about switch/case that is explicitly intended to fall through.
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#define FL_FALLTHROUGH __attribute__ ((fallthrough));
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// This method is made static to force making register Y available to use for data on AVR - if the method is non-static, then
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// gcc will use register Y for the this pointer.
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static void /*__attribute__((optimize("O0")))*/ /*__attribute__ ((always_inline))*/ showRGBInternal(PixelController<RGB_ORDER> & pixels) {
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uint8_t *data = (uint8_t*)pixels.mData;
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data_ptr_t port = FastPin<DATA_PIN>::port();
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data_t mask = FastPin<DATA_PIN>::mask();
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uint8_t scale_base = 0;
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// register uint8_t *end = data + nLeds;
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data_t hi = *port | mask;
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data_t lo = *port & ~mask;
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*port = lo;
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// the byte currently being written out
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uint8_t b0 = 0;
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// the byte currently being worked on to write the next out
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uint8_t b1 = 0;
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// Setup the pixel controller
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pixels.preStepFirstByteDithering();
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// pull the dithering/adjustment values out of the pixels object for direct asm access
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uint8_t advanceBy = pixels.advanceBy();
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uint16_t count = pixels.mLen;
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uint8_t s0 = pixels.mScale.raw[RO(0)];
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uint8_t s1 = pixels.mScale.raw[RO(1)];
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uint8_t s2 = pixels.mScale.raw[RO(2)];
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#if (FASTLED_SCALE8_FIXED==1)
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s0++; s1++; s2++;
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#endif
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uint8_t d0 = pixels.d[RO(0)];
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uint8_t d1 = pixels.d[RO(1)];
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uint8_t d2 = pixels.d[RO(2)];
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uint8_t e0 = pixels.e[RO(0)];
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uint8_t e1 = pixels.e[RO(1)];
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uint8_t e2 = pixels.e[RO(2)];
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uint8_t loopvar=0;
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// This has to be done in asm to keep gcc from messing up the asm code further down
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b0 = data[RO(0)];
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{
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LDSCL4(b0,O0) PRESCALEA2(d0)
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PRESCALEB4(d0) SCALE02(b0,0)
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RORSC04(b0,1) ROR1(b0) CLC1
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SCROR04(b0,2) SCALE02(b0,3)
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RORSC04(b0,4) ROR1(b0) CLC1
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SCROR04(b0,5) SCALE02(b0,6)
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RORSC04(b0,7) ROR1(b0) CLC1
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MOV_ADDDE04(b1,b0,d0,e0)
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MOV1(b0,b1)
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}
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{
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// while(--count)
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{
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// Loop beginning
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DNOP;
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LOOP;
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// Sum of the clock counts across each row should be 10 for 8Mhz, WS2811
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// The values in the D1/D2/D3 indicate how many cycles the previous column takes
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// to allow things to line back up.
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//
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// While writing out byte 0, we're loading up byte 1, applying the dithering adjustment,
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// then scaling it using 8 cycles of shift/add interleaved in between writing the bits
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// out. When doing byte 1, we're doing the above for byte 2. When we're doing byte 2,
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// we're cycling back around and doing the above for byte 0.
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|
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// Inline scaling - RGB ordering
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// DNOP
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HI1 _D1(1) QLO2(b0, 7) LDSCL4(b1,O1) _D2(4) LO1 PRESCALEA2(d1) _D3(2)
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HI1 _D1(1) QLO2(b0, 6) PRESCALEB4(d1) _D2(4) LO1 SCALE12(b1,0) _D3(2)
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|
HI1 _D1(1) QLO2(b0, 5) RORSC14(b1,1) _D2(4) LO1 RORCLC2(b1) _D3(2)
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|
HI1 _D1(1) QLO2(b0, 4) SCROR14(b1,2) _D2(4) LO1 SCALE12(b1,3) _D3(2)
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|
HI1 _D1(1) QLO2(b0, 3) RORSC14(b1,4) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 2) SCROR14(b1,5) _D2(4) LO1 SCALE12(b1,6) _D3(2)
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|
HI1 _D1(1) QLO2(b0, 1) RORSC14(b1,7) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 0)
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|
switch(XTRA0) {
|
|
case 4: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 3: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 2: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 1: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0)
|
|
}
|
|
MOV_ADDDE14(b0,b1,d1,e1) _D2(4) LO1 _D3(0)
|
|
|
|
HI1 _D1(1) QLO2(b0, 7) LDSCL4(b1,O2) _D2(4) LO1 PRESCALEA2(d2) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 6) PSBIDATA4(d2) _D2(4) LO1 SCALE22(b1,0) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 5) RORSC24(b1,1) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 4) SCROR24(b1,2) _D2(4) LO1 SCALE22(b1,3) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 3) RORSC24(b1,4) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 2) SCROR24(b1,5) _D2(4) LO1 SCALE22(b1,6) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 1) RORSC24(b1,7) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 0)
|
|
switch(XTRA0) {
|
|
case 4: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 3: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 2: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 1: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0)
|
|
}
|
|
|
|
// Because Prescale on the middle byte also increments the data counter,
|
|
// we have to do both halves of updating d2 here - negating it (in the
|
|
// MOV_NEGD24 macro) and then adding E back into it
|
|
MOV_NEGD24(b0,b1,d2) _D2(4) LO1 ADDDE1(d2,e2) _D3(1)
|
|
HI1 _D1(1) QLO2(b0, 7) LDSCL4(b1,O0) _D2(4) LO1 PRESCALEA2(d0) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 6) PRESCALEB4(d0) _D2(4) LO1 SCALE02(b1,0) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 5) RORSC04(b1,1) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 4) SCROR04(b1,2) _D2(4) LO1 SCALE02(b1,3) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 3) RORSC04(b1,4) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 2) SCROR04(b1,5) _D2(4) LO1 SCALE02(b1,6) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 1) RORSC04(b1,7) _D2(4) LO1 RORCLC2(b1) _D3(2)
|
|
HI1 _D1(1) QLO2(b0, 0)
|
|
switch(XTRA0) {
|
|
case 4: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 3: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 2: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0) FL_FALLTHROUGH
|
|
case 1: _D2(0) LO1 _D3(0) HI1 _D1(1) QLO2(b0,0)
|
|
}
|
|
MOV_ADDDE04(b0,b1,d0,e0) _D2(4) LO1 _D3(5)
|
|
ENDLOOP5
|
|
}
|
|
DONE;
|
|
}
|
|
|
|
#if (FASTLED_ALLOW_INTERRUPTS == 1)
|
|
// stop using the clock juggler
|
|
TCCR0A &= ~0x30;
|
|
#endif
|
|
}
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
FASTLED_NAMESPACE_END
|
|
|
|
#endif
|